1) Field of the Invention
The present invention relates to a data storage apparatus (disk array apparatus). In particular, the invention relates to the technology for controlling a cash memory in a control apparatus that performs processing to a storage apparatus in accordance with a processing request from an upper apparatus.
2) Description of the Related Art
With a recent tendency of digitizing various types of data for its use on computers, there exits an increasing importance of data input/output apparatuses (data storage apparatuses) that are capable of efficiently storing a great mount of data with high reliability, independent from host computers executing processing to data.
As such a data storage apparatus, a disk array apparatus, which is formed of a great number of disks (for example, magnetic tapes and optical disks) and a disk controller that controls such a great number of disks, has been used. This disk array apparatus is capable of controlling the great number of disks thereof in response to disk access requests from an upper apparatus (host computer).
Here, FIG. 26 illustrates a construction of a storage system 110 having a previous disk array apparatus 100. The previous storage system 110 is formed of the disk array apparatus 100 and a host (HOST) 111, as an upper apparatus, which issues access requests to the disk array apparatus 100.
The disk array apparatus 100 is formed of a data storage apparatus (DE: Device Enclosure) 101 on which are mounted multiple disks (not illustrated; non-volatile media) storing data therein and a control apparatus (CE: Controller Enclosure) 102 on which are mainly mounted communication modules for communicating with the control apparatus and the host apparatus (host 111).
In this instance, the number of disks mounted on the storage apparatus 101 increases as the construction scale of the disk array apparatus 100 becomes greater.
Here, the control apparatus 102 has more than one (here, two) controller module (CM: Controller Module) 103a and 103b. In the following description, the controller modules will be called “CMs 103” when no distinction is made between the CM 103a and the CM 103b. 
Each of the host 111 and the CM 103 are coupled to each other by means of coupling the interfaces 112a through 112d [expressed as “CH” (Channel Interface) in the figure] of the host 111 with the CAs (Channel Adaptors) 104a through 104d, respectively.
Further, the CM 103 is coupled to the DE 101 through DAs (Disk Adapters) 105a through 105d. 
Each of the CMs 103a and 103b includes cache memories (expressed as “Memory” in the figure) 106a and 106b, which are volatile media, and two CPUs (Central Processing Units) 107a and 107b, and 108a and 108b. In this instance, in the following description, the cache memories will be called the “cache memories 106” when no distinction is made between the cache memories 106a and 106b, and the CPUs will be called the “CPU 107” and the “CPU 108” when no distinction is made between the CPUs 107a and 107b or between the CPUs 108a and 108b. 
Upon generation of a data access (read/write request) from the host 111, the CMs 103 controls the DE 101 in accordance with the request.
When the host 111 sends a data writing request, the CPU 107 and the CPU 108 of the CMs 103 control data write processing of the DE 101 to a disk.
Further, upon issuance of a data reading request from the host 111, the CPU 107 and the CPU 108 of the CMs 103 send the data to the host 111 when the data is present in the cache memories 106. Contrarily, when the data is absent in the cache memories 106, the CPU 107 and the CPU 108 read the data from the DE 101 and sends the data to the host 111.
In this instance, the CPUs 107 and 108 registers the data read from the DE 101 in the cache memories 106. That is, the CPUs 107 and 108 function also as a controller that controls the cache memories 106.
Here, upon accessing (a reading request) from the host 111, when the requested data is present in the cache memories 106 of the CMs 103, the disk array apparatus 100 is capable of responding to the host 111 in high speed.
However, when the request data is not present in the cache memories 106 of the CMs 103, the disk array apparatus 100 must read the data from the DE 101, so that the response speed to the host 111 is decreased.
In addition, recently, the storage capacity of disks (for example, hard disks) of the DE 101 of a disk array apparatus 100 has been increased, and the maximum storage capacity is increased up to the petabyte order. Although the storage capacity of a cache memory 106 has also been increased, it still stays at the gigabyte order, so that it has not utterly reached the storage capacity of the disks of the DE 101.
Hence, in such a disk array apparatus 100, the following methods (1) through (3) have been employed as a method for controlling data to be registered (expanded) in cache memories 106 for the purpose of improving the response ability.
(1) Data is expanded in/removed (released) from cache memories 106 by using the LRU (Least Recently Used) logic.
(2) Data to which accesses are made at a high frequency is resident, or is remained with precedence, in cache memories 106.
(3) In accordance with access requests in the past, data is prior read (obtained) to cache memories 106 (see, for example, the following patent documents 1 through 3).